1. Field of the Invention
The present invention relates to integrated semiconductor memories using dynamic RAMs (dRAMs) containing dynamic memory cells for destructive readout.
2. Description of the Related Art
Recently many inventions and developments have been made to speed up semiconductor memories. The semiconductor memories include dRAMs and sRAMs (static RAMs). The dRAMs are superior to the sRAMs in storage capacity and cost, but inferior in speed. The reason why the dRAMs are inferior to the sRAMs in speed is that the dRAMs are increased in integration density by the use of an address multiplexing method in order to decrease their cost per bit. The fact that dRAMs need refreshing and bit-line precharging because they are of destructive-read type may also be attributed to their low-speed operation. With computers using the sRAMs as their main memories, their machine cycle is determined only by an access time to the sRAM. Where the dRAMs are used as main memories, the machine cycle is determined by their access time and bit-line precharging time.
For that reason, in the conventional dRAMs, various operation modes, such as a page mode, a nibble mode and a static column mode, have been developed to shorten the access time.
However, a problem with the conventional dRAMs is that, even if the access time is reduced in a normal access mode, the cycle time is not so reduced. For example, with a 1M-bit dRAM having an access time of 100 nsec in the normal access mode, the cycle time is 190 nsec in its specification because it is a sum of an active time and the precharging time. Even if the access time is reduced by half, the cycle time will not be halved unless the precharging time is also reduced by half. The difficulty in reducing the precharging time is due not only to the fact that the capacitive loads of bit lines to be charged have been increased to increase the storage capacity of the dRAMs, but also to the fact that the bit lines are precharged and equalized during a precharging period in which an RAS signal (row address strobe signal for loading the row address into the memory device) goes from a logic "0" to a logic "1", not during an active period to read or write data.
Where semiconductor memories are installed in computers, the length of machine cycle is an important factor in the performance of the computers. In the static RAMs, since the access time and the cycle time coincide with each other, the reduction of the access time will also reduce the machine cycle. In the dynamic RAMs, however, the reduction of the access time alone will not lead to the reduction of the machine cycle.
In the conventional dRAMs of address multiplexing type, there is no distinction between a read cycle and a write cycle because an address data selector is controlled by a CAS signal (column address strobe for loading the column address into the memory device) only. That is, during an active cycle, a row address strobe (RAS) is input into the dRAM prior to the CAS. The row address and the column address are issued in this sequence from the address data selector and then entered into a dRAM chip. To secure operational margin surely, a certain time is needed from when the RAS is made active until the CAS is made active. It is thus difficult to shorten the cycle time of the dRAMs and hence the machine cycle of computers using the dRAMs.
As described above, the conventional dRAMs have a problem that the reduction of the access time does not lead to the reduction of the cycle time, and thus the machine cycle of the computers using the dRAMs cannot be reduced.